The present invention concerns a semiconductor device and a method of manufacture thereof; and, more in particular, it relates to a technique which is effective for application to the manufacture of a semiconductor device having an SRAM (Static Random Access Memory) in which a memory cell is constituted by using vertical-type MISFETs.
In an SRAM which represents a kind of general-purpose large capacity semiconductor memory device, a memory cell is constituted, for example, with four n-channel type MISFETs (Metal-Insulator-Semiconductor-Field-Effect-Transistor) and two p-channel type MISFETs. However, in the so-called complete CMOS (Complementary-Metal-Oxide-Semiconductor) type SRAM of this type, since six MISFETs are arranged in a planar manner on the main surface of a semiconductor substrate, it is difficult to reduce the size of the memory cell. That is, in the complete CMOS type SRAM requiring p- and n-type well regions for forming the CMOS and a well isolation region for isolation between a n-channel type MISFET and a p-channel type MISFET, it is difficult to reduce the size of the memory cell.
For example, Japanese Patent Application laid-open No. Hei 9(1997)-283462 discloses a technique which consists of forming, in an insulation film deposited on a semiconductor substrate, a contact hole reaching a source-drain diffusion layer formed at an upper surface thereof with a titanium silicide layer, then selectively growing a silicon film in the contact hole, further forming thereover a titanium film, forming silicide to the boundary between the silicon film and the titanium film, and then depositing an aluminum film. (Patent document 1)
Further, for example, Japanese Patent Application laid-open No. Hei 8(1996)-204009 discloses a technique which consists of ion implanting silicon to a high melting metal film to a contact boundary between a high melting metal film and a semiconductor prior to the formation of the silicide layer, thereby lowering the temperature of heat treatment for silicidation. (Patent document 2)
Further, for example, Japanese Patent Application laid-open No. Hei 5(1993)-315333 discloses a technique which consists of introducing impurities for forming a conduction type identical with that of polycrystal silicon into a silicide layer of a structure having the silicide layer on a polycrystal silicon film, thereby suppressing diffusion of impurities in the polycrystal silicon. (Patent document 3)
Further, for example, Japanese Patent Application laid-open No. Hei 8(1996)-264536 discloses a technique, for use in a constitution in which a polycrystal silicon film is joined to a high melting metal silicide film, which consists of forming a high concentration region by implanting silicon ions to a portion of the high melting metal silicide film that is joined with the polycrystal silicon film, thereby suppressing suction of impurities from the polycrystal silicon film. (Patent document 4)
[Patent Document 1]
    Japanese Patent Application laid-open No. Hei 9(1997)-283462[Patent Document 2]    Japanese Patent Application laid-open No. Hei 8(1996)-204009[Patent Document 3]    Japanese Patent Application laid-open No. Hei 5(1993)-315333[Patent Document 4]    Japanese Patent Application laid-open No. Hei 8(1996)-264536